With enhancement of degree of integration and formation of more multi-layer interconnections in the semiconductor devices, storage capacities of memory devices have been greatly increased. This is supported by the advancement in the fine process technologies. In spite of formation of more multilayer interconnections, however, the chip size becomes larger and the number of processing steps is increased with the advancement in the fine process technologies, resulting in increase of chip cost. Under such circumstances, chemical mechanical polishing technique has been introduced into polishing of process films or the like and is paid attention. By adopting this chemical mechanical polishing technique, a large number of fine process technologies such as planarization have been embodied.
As one of such fine process technologies, shallow trench isolation, namely, so-called STI technology is known. In the STI technology, chemical mechanical polishing is carried out in order to remove an excess of an insulating layer formed on a wafer substrate. In this chemical mechanical polishing process, planarity of the polished surface is important, and on this account, various polishing agents have been studied.
For example, Japanese Patent Laid-Open Publication No. 5-326469/1993 and Japanese Patent Laid-Open Publication No. 9-270402/1997 disclose that by the use of an aqueous dispersion using ceria as abrasives in the chemical mechanical polishing step of STI, a high removal rate is achieved and a polished surface having relatively few polishing scratches is obtained. In Japanese Patent Laid-Open Publication No. 5-326469/1993, however, there is a problem that a large number of polishing scratches occur because inorganic particles having a large diameter are used as abrasives. In Japanese Patent Laid-Open Publication No. 9-270402/1997, there is a problem that a removal rate is slow because cerium oxide particles having a small average particle diameter are used as abrasives.
In recent years, as much finer and more multilayer interconnections of semiconductor devices have been developed, further improvement of yield or throughput of the semiconductor devices has been required. With such requirement, polishing that causes substantially no polishing scratches on a polished surface after chemical mechanical polishing and that provides a high removal rate has been desired.
With regard to decrease of polishing-scratches on the polished surface, it has been reported that surfactants, such as chitosan acetate, dodecylamine and polyvinyl pyrrolidone, are effective (see, e.g., Japanese Patent Laid-Open Publication No. 2000-109809, Japanese Patent Laid-Open Publication No. 2001-7061 and Japanese Patent Laid-Open Publication No. 2001-185514). According to these reports, the above surfactants are effective for the decrease of polishing scratches. However, the removal rate is lowered, and improvement of throughput has not been achieved yet.
Further, with regard to a polishing method in order to decrease polishing scratches on the polished surface and to provide a high removal rate, it has been reported that a polishing method in which cerium oxide particles are moderately aggregated in a specific average particle diameter and the aggregates are maintained in stable state is effective (see, e.g., Japanese Patent Laid-Open Publication No. 2000-252245). Moreover, it has been reported that a aqueous dispersion comprising inorganic particles and polymer particles having an average particle diameter not larger than that of the inorganic particles, and a aqueous dispersion comprising inorganic abrasives and anionic organic particles are effective (see, e.g., Japanese Patent Laid-Open Publication No. 2002-204353 and Japanese Patent Laid-Open Publication No. 2001-323256). In some materials of polished surfaces, however, by the use of the method or the aqueous dispersions, a large number of polishing scratches sometimes occur or a sufficient removal rate cannot be sometimes achieved.